Your guide to Intel Core 2

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Mobile, server, and the future
Core processor was a mobile CPU, the new line-up starts with desktop and server parts – previously codenamed Conroe and Woodcrest, respectively – followed by the mobile CPUs in August or September.

Being based on the same micro-architecture, Woodcrest – now renamed the Xeon 5100 series – ups the performance via an increased maximum frequency of 3GHz, and a faster front side bus speed of 1333MHz for the top-end parts.
Merom – currently referred to by Intel as Core 2 Duo for laptops – will sport more complex power-specific enhancements, which may be the reason for its delay. Its other specifications are broadly the same, with 2MB and 4MB Level 2 cache variants, but with 667MHz FSB and lower initial clock speeds.

The lack of HyperThreading on the Extreme Edition X6800 has led to strong rumours of a faster Extreme part soon, with both a higher clock speed, 1333MHz FSB and HyperThreading. This will likely soon be replaced by Kentsfield, the quad-core desktop part, which we’ve already seen running on an Intel demonstration system. Again, this will be an LGA775 part and probably a drop-in replacement that will run happily on existing 975X and P965 chipsets.

The performance enhancements
The biggest single contributor to the improved performance of Core 2 is ‘wide dynamic execution’. ‘Wide’ refers to the fact that every stage of the instruction fetch, decode and execution system is wider than before, allowing it to cope with up to four standard instructions simultaneously. Previous designs had a three-wide instruction engine. ‘Dynamic’ covers the sophisticated schemes the CPU uses to operate speculative and out-of-order execution and branch prediction. The system owes a lot to the old NetBurst architecture, but the very deep 31-instruction pipeline – which led to a severe performance hit on a branch misprediction as the pipeline had to be cleared and refilled – is down to a depth of 14. The out-of-order execution engine has been given more depth, though: with deeper instruction buffers – 96 instructions rather than the 64 of Core – Core 2 is able to search further ahead to find ‘in-flight’ instructions it can execute in parallel to keep all four execution paths fully utilised.

Advanced smart cache
As with Core in notebooks, Core 2’s Level 2 cache is shared between the two cores. This gives two benefits over standard per-core cache. First, it avoids a situation where one core is idling while the other core is labouring along at full pelt but unable to access the spare cache. The ability for one core to use all the cache effectively gives you a single-core CPU with 4MB when the situation demands. It’s interesting to note that the two cores don’t arbitrate for cache allocation: they simply compete for it, grabbing as much as they need when they can, so long as it isn’t being used by the other core. Intel says this has turned out to be more efficient and effective than a complex arbitration system. A secondary benefit is that cache use is optimised, since if both cores need access to the same data it doesn’t need to be loaded twice. The ‘advanced’ prefix, which has appeared since the system debuted on the Core, is due to a doubling in bandwidth for transfers between Level 1 and Level 2 cache.

Smart memory access
It’s a common criticism of the Intel platform architecture that the memory subsystem is both bottlenecked and a victim of high latency. The shared front side bus represents the bottleneck; the need to communicate with main memory via the north bridge chip increases latency. AMD cuts out all this with its on-chip integrated memory controller and dedicated memory interface. But Intel has largely overcome the problem with its ‘Smart memory access’ design. Rather than relying on low latency to grab data from main memory on a just-in-time basis, the system loads data into the Level 2 cache before it’s needed. The upshot is that latency isn’t an issue, since if the data required by the CPU is already loaded into the Level 2 cache, main-memory latency is hidden. The system effectively increases the bandwidth of the main memory interface itself by making maximum use of available throughput, continually pre-loading. That’s not to say increased memory bandwidth isn’t needed; the new ICH8 memory controller hub, which supports 800MHz DDR2 RAM, made a notable difference in our tests: swapping 800MHz memory for 667MHz DIMMs brought the application benchmark score for the E6700 down from 1.65 to 1.55; a 6 percent drop.

Advanced digital media boost
This is the latest catch-all term for all the specialist SIMD (single instruction, multiple data) instructions and registers, now incorporating MMX, SSE, SE2 and SSE3. There are no new instructions, but performance has been increased by a tweak to allow one complete 128-bit execution step in a single clock cycle rather than two, effectively doubling the speed of 128-bit operations.

Intelligent power capability
Decreasing the frequency is one reason why its power consumption is much lower than previous Intel desktop chips, but there are other enhancements at the logic level. It has finer granularity in its ability to shut down the parts of the processor that aren’t being used at any given time, making for much reduced power consumption in average use. There’s always a slight performance hit when powering areas of the processor back up, though, hence not all the power-saving features of the mobile version are in the desktop chips. The TDP (thermal design power) of the E6700 is 65W; that’s half the rating of a Pentium D 960. Intel hasn’t yet released the TDP figures for the other desktop parts, but based on published figures for the Woodcrest Xeons, the E6400 should come in around the 40W mark, and the Extreme Edition X6800 at about 80W, which is still 50W lower than the 3.73GHz 965 Extreme Edition part.

Conclusion
The basic models are very fast. The high-end ones are faster still. All are low power. And, tellingly for AMD, the fastest score we’ve seen from an FX-62 system is 1.45 – some 12 percent slower than the E6700 here. The only disappointment with Core 2 is that there’s nothing bad we can say.

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